1. Field of the Invention
This invention relates to a dynamic RAM (Random Access Memory) with a single transistor storage cell, and more particularly to a sense amplifier circuit used in the dynamic RAM.
2. Description of the Prior Art
Generally, in a RAM utilizing the 1 transistor/cell system, the voltage changes occurring in the data lines are minute, and therefore a "sense amplifier circuit" (output detector) for the evaluation and regeneration of a data, which can detect the read-out data with satisfactory sensitivity and amplify this data reliably is necessary.
Some improvements for the above-mentioned sense amplifier circuit have recently been made, for example see U.S. Pat. No. 3,774,176, issued on Nov. 20, 1973.
In this patent, the sense amplifier circuit is practiced by using a flip-flop circuit having a pair of input nodes, which are connected to data lines. Furthermore a semiconductor switch, for instance a MOS FET, is connected between the nodes operable to place the nodes at the same potential.
In the above-mentioned Dynamic RAM, the sense amplifier circuit can be so designed as to have a sensitivity of 200 to 300 mV, and can be made to perform stabilized reading out and writing in operation, but it has the following defects. Firstly, during amplification of the read-out and during writing in data, direct current flows between the power sources of the sense amplifier circuit, and therefore the power consumed becomes large. Secondly, the above-mentioned sense amplifier circuit operates statically, therefore the conductance of load transistors cannot be made large, and accordingly the speed during amplification of the data becomes slow. Thirdly, when data is being sensed, the voltages of the data lines are reduced to the threshold voltage levels of the switching MOS transistors each of whose gate electrodes are respectively cross-connected to the other transistor's drain electrodes. Furthermore, the stray capacities of the data lines are large (generally diffusion layers are used as the data line in order to make the figure of merit of the memory cells satisfactory), and therefore the voltage change of data line in read-out operation becomes small. Accordingly in order to make the voltage change of the data line large, the capacity of the capacitor of the memory cell was made large, so that there was the defect that the degree of the integration was lowered.